Design and simulation results of fully integrated 5-GHz CMOS LNAs are presented in this paper. Three different input impedance matching techniques are considered. Using a simple L-C network, the parasitic input resistance of a MOSFET is converted to a 50Ω resistance. As it is analytically proven, that is because the former methods enhance the gain of the LNA by a factor that is inversely proportional to MOSFET’s input resistance. The effect of each input impedance matching on the amplifier’s noise figure and gain is discussed. By employing the folded cascode configuration, these LNAs can operate at a reduced supply voltage and thus lower power consumption. To address the issue of nonlinearity in design of low voltage LNAs, a new linearization technique is employed. As a result, the IIP3 is improved extensively without sacrificing other parameters. These LNAs consume 1.3 mW power under a 0.6 V supply voltage.

Scaling challenges and limitations of conventional silicon transistors have led the designers to apply novel nano-technologies. One of the most promising and possible nano-technologies is CNT (Carbon Nanotube) based transistors. CNFET have emerged as the more practicable and promising alternative device compared to the other nanotechnologies. This technology has higher efficiency compared to the silicon-based MOSFET and is appropriate for high-frequency applications. Full Adder cell is the essential core and the building block of most arithmetic circuits and is placed on most parts of their critical paths. In this paper, power-efficient CNFET (Carbon Nanotube Field Effect Transistor) based Full Adder cell is proposed. This design is simulated in several supply voltages, frequencies and load capacitors using HSPICE circuit simulator. Considerable improvement is achieved in terms of power and PDP (Power-Delay-Product) in comparison with other classical CNFET-based designs, in the literature. Our proposed Full Adder can also drive large load capacitance and works properly in low supply voltages.

Shaft position sensing is an essential part of switched reluctance (SR) motor drive In order to synchronize the pulses of phase current with the period of rising inductance of the proper motor phase. Direct sensors such as, Hall effect and optical encoder are commonly used in SR motors. The purpose of this paper is to present an indirect shaft positioning sensing known as "sensor less” control for switched reluctance motor. It uses stator inductance measurement technique by multiplexing each phase inductance to predict the rotor position and also using a micro controller to produce proper gate pulses for the motor phases. This circuit has the ability of controlling the proper advancement of firing time for each power transistor (adjusting the dwell angle) in the drive circuit either manually or automatically for different speeds. It has also the option of selecting the direction of rotation for the motor and uses a PWM scheme for variable speed as well as, a full stop braking system. This control circuit in conjunction with a two switch per phase configuration converter drive has been tested on a 35W, 12V; 3-phase switched reluctance motor and the test results are presented.

In this paper, a novel low voltage low power current buffer was presented. The proposed structure was implemented in CMOS technology and is the second generation of OCB (orderly current buffer) called OCBII. This generation is arranged in single inputsingle output configuration and has modular structure. It is theoretically analyzed and the formulae of its most important parameters are derived. Pre and Post-layout plus Monte Carlo simulations were performed under  0. 75 V by Cadence using TSMC 0. 18 μ m CMOS technology parameters up to 3rd order. The proposed structure could expand and act as a dual output buffer in which the second output shows extremely high impedance because of its cascode configuration. The results prove that OCBII makes it possible to achieve very low values of input impedance under low supply voltages and low power dissipation. The most important parameters of 1st, 2nd and 3rd orders, i. e. input impedance (Rin),-3 dB bandwidth (BW), power dissipation (Pd) and output impedance (Ro) were found respectively in Pre-layout plus Monte Carlo results as: 1st order: Rin (52. 4 Ω ), BW (733. 7 MHz), Pd (225. 6 μ W), Ro (105. 6 kΩ ) 2nd order: Rin (3. 8 Ω ), BW (576. 4 MHz), Pd (307 μ W), Ro (106. 4 kΩ ) 3rd order: Rin (0. 34 Ω ), BW (566. 9 MHz), Pd (535. 6 μ W), Ro (118. 2 kΩ ) And in Post-layout plus Monte Carlo results as: 1st order: Rin (59. 9 Ω ), BW (609. 6 MHz), Pd (212. 4 μ W), Ro (106. 9 kΩ ) 2nd order: Rin (11. 3 Ω ), BW (529. 3 MHz), Pd (389. 9 μ W), Ro (109. 8 kΩ ) 3rd order: Rin (5. 8 Ω ), BW (526. 5 MHz), Pd (514. 5 μ W), Ro (125. 5 kΩ ) Corner cases simulation results are also provided indicating well PVT insensitivity advantage of the block.

Photovoltaic (PV) panels rely on environmental conditions such as irradiation or temperature, and thus they require an interface boost converter. Non-isolated DC-DC boost converters have a lower volume, lower costs and lower power dissipation compared with isolated converters. In this study, a novel high efficiency non-isolated DC-DC boost converter is proposed to be used in PV systems. The converter includes only one semiconductor switch which causes lower switching losses. The main advantages of the proposed converter include low input current ripples, low voltage stress on semiconductor switches, high efficiency and low conduction losses. Moreover, maximum power is achieved from PV panels. A prototype of the proposed converter has been built, and experimental results are presented which explicitly validate theoretical results, suggesting that this boost converter is desirable for PV applications.